From 9bb539c1a0333a5648266f6d2b8982cee5f1143a Mon Sep 17 00:00:00 2001
From: Kytezign <Kytezign@gmail.com>
Date: Wed, 5 Aug 2026 19:58:37 -0700
Subject: [PATCH] Fix bug doing read modify write on set only registers

This bug can be especially bad on the NVIC_ICER where a read, modify, write can actually disable all previously enabled interrupts (rather than just the intended interrupt)
---
 core/src/cpus/cortex_m/m0plus.zig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/core/src/cpus/cortex_m/m0plus.zig b/core/src/cpus/cortex_m/m0plus.zig
index 164d27741..006408909 100644
--- a/core/src/cpus/cortex_m/m0plus.zig
+++ b/core/src/cpus/cortex_m/m0plus.zig
@@ -172,11 +172,11 @@ pub const NestedVectorInterruptController = extern struct {
     }
 
     pub fn enable(nvic: *volatile NestedVectorInterruptController, num: comptime_int) void {
-        nvic.ISER |= 1 << num;
+        nvic.ISER = 1 << num;
     }
 
     pub fn disable(nvic: *volatile NestedVectorInterruptController, num: comptime_int) void {
-        nvic.ICER |= 1 << num;
+        nvic.ICER = 1 << num;
     }
 
     pub fn is_pending(nvic: *volatile NestedVectorInterruptController, num: comptime_int) void {
@@ -184,11 +184,11 @@ pub const NestedVectorInterruptController = extern struct {
     }
 
     pub fn set_pending(nvic: *volatile NestedVectorInterruptController, num: comptime_int) void {
-        nvic.ISPR |= 1 << num;
+        nvic.ISPR = 1 << num;
     }
 
     pub fn clear_pending(nvic: *volatile NestedVectorInterruptController, num: comptime_int) void {
-        nvic.ICPR |= 1 << num;
+        nvic.ICPR = 1 << num;
     }
 };