Issues

• [ExportVerilog] Missing whitespace after escaped package identifiers

  ExportVerilog
  llvm/circt#11208 · Filter by author teqdruid opened on Sep 29, 2026
  1

• [PyCDE] Support importing an sv.package without re-emitting it

  enhancementPyCDE
  llvm/circt#11200 · Filter by author teqdruid opened on Sep 28, 2026

• [FIRRTL] LowerToHW: exceeding IntegerType bitwidth limits causes an assert

  FIRRTL
  Bug

  llvm/circt#11195 · Filter by author youngar opened on Sep 28, 2026

• [PyCDE] Constructing a value of a TypeAlias type aborts with an LLVM assertion

  PyCDE
  llvm/circt#11170 · Filter by author teqdruid opened on Sep 24, 2026

• [PyCDE] publishing pipeline is flakey

  PyCDE
  llvm/circt#11160 · Filter by author teqdruid opened on Sep 24, 2026

• [FIRRTL] LowerSignatures reverses strictconnect direction for output fields in analog-containing bundles

  llvm/circt#11151 · Filter by author kimdh727 opened on Sep 22, 2026

• [circt-synth] Use circt-synth in OpenROAD-flow-scripts

  Synth
  llvm/circt#11143 · Filter by author uenoku opened on Sep 21, 2026

• [Moore] Some packed aggregate references fail to lower

  llvm/circt#11141 · Filter by author SathsaraGeeth opened on Sep 19, 2026

• [SV][ExportVerilog] Determine sv.package ordering via dependence analysis

  ExportVerilogSV
  llvm/circt#11139 · Filter by author teqdruid opened on Sep 18, 2026

• [ImportVerilog] String casts to packed byte arrays fail

  llvm/circt#11133 · Filter by author dagronlund opened on Sep 16, 2026

• [ImportVerilog] Support concurrent cover property and cover sequence statements

  llvm/circt#11128 · Filter by author dagronlund opened on Sep 16, 2026

• [ImportVerilog] Support assignment patterns as assignment destinations

  llvm/circt#11123 · Filter by author dagronlund opened on Sep 15, 2026

• [ImportVerilog] Resolve hierarchical outputs from expanded interfaces

  llvm/circt#11122 · Filter by author dagronlund opened on Sep 15, 2026

• [ImportVerilog] Support connected interface-array ports

  llvm/circt#11121 · Filter by author dagronlund opened on Sep 15, 2026

• [HW][ExportVerilog] Union Bitcast Layout: Left or Right Jusitfied

  llvm/circt#11120 · Filter by author fzi-hielscher opened on Sep 15, 2026
  2

• [FIRRTL] User assertions reading ports produce SV reading values from equivalent wire not port; no mechanism to express intent

  FIRRTL
  llvm/circt#11114 · Filter by author dtzSiFive opened on Sep 14, 2026

• [CalyxToHW] Fails to lower 1D calyx.seq_mem to HW: "couldn't convert to core primitive" / "incorrect number of address ports"

  llvm/circt#11111 · Filter by author Jimmy-Hu opened on Sep 12, 2026
  2

• [circt-verilog][RegOfVecToMem] Fail to recognize SRAM with mask

  llvm/circt#11097 · Filter by author uenoku opened on Sep 10, 2026
  3

  

• [lower-calyx-to-hw] Segmentation fault when calyx.invoke refCellsMap points to local instances instead of ref cells

  llvm/circt#11087 · Filter by author Jimmy-Hu opened on Sep 8, 2026

• [FIRRTL] CheckCombLoops crashes on a forceable register reference cast to a layer-colored RWProbe

  llvm/circt#11085 · Filter by author Clo91eaf opened on Sep 8, 2026

• [SV] Rename "sym_name" in GenerateOp to something different

  llvm/circt#11079 · Filter by author uenoku opened on Sep 3, 2026

• [FIRRTL] zero-width aggregate consumers crash or produce invalid IR

  FIRRTL
  llvm/circt#11063 · Filter by author youngar opened on Aug 28, 2026

• [ImportVerilog] Streaming operators fail on unpacked arrays

  good first issueImportVerilog
  llvm/circt#11028 · Filter by author fabianschuiki opened on Aug 19, 2026
  6

• [Moore] Missing conversions to open array types

  good first issueMoore
  llvm/circt#11027 · Filter by author fabianschuiki opened on Aug 19, 2026
  4

  

• [ImportVerilog] Don't convert lvalues

  ImportVerilog
  llvm/circt#11026 · Filter by author fabianschuiki opened on Aug 19, 2026