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RISC-V Processor in Verilog

This is a project completed as part of Brown's ENGN1640 course. There was no stencil, and everything was written from scratch without the use of AI tools. This has been one of my favorite projects I've done in school thus far, so I thought it fitting to showcase on my Github.

If I find the time, I'd like to make a few revisions. For one thing, I'd like to clean up the code and organize it a little more. I am also considering (as a learning experience) extending the project incorporate peripherals and clock domain crossing.

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A pipelined RISC-V processor written in Verilog.

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