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DMA6: mask CHCR writes, start the OTC on bits 24 and 28 - #2475
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Only bits 24, 28 and 30 of D6_CHCR are writable and bit 1 reads 1. The OTC runs when 24 and 28 are both set, whatever the other bits; 24 alone stays busy. MADR and BCR are not written back. Measured on SCPH-1000, SCPH-5501 and SCPH-9002; tests in nugget tests/dma.
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dma6()only ran onchcr == 0x11000002, so0x11000000(what psx-spx documents as enough) did nothing, and any other value with bit 24 set completed instantly with an IRQ and no OT written. On SCPH-1000, SCPH-5501 and SCPH-9002 the writable bits are 24, 28 and 30, bit 1 reads 1, the OTC runs when 24 and 28 are both set, and 24 alone stays busy forever. CHCR writes are now masked to that, and DMA6 skips the generic MADR/BCR writeback, which had been adding 0x200000 to MADR and zeroing BCR.DMA6 only on purpose; the other channels' CHCR masks and DREQ behaviour are a bigger rework of the DMA dispatch. Not modelled either: a transfer latched with ch6 disabled starts when DPCR enables the channel (on hardware it does; that test stays
CESTER_MAYBE_TEST).The pin points at nugget
dma6-otc-strict, which turns the newtests/dmacases on underPCSX_TESTS. pcsx-redux/nugget#272 merges them as hardware-only, since nugget CI runs against the current dev build.