Vias on wrong layers

[qaqcvc]

First of all, I would like to thank all the contributors for this wonderful tool. It is a lifesaver!

In this practive, I am tring to output the pcb with micro layers from 1-2 and 23-24, as well as burried vias from 2-23. But the output shows wrong vias locations:

Is it a bug, or do I possibly set smethong wrong?
I have checked the setting of vias in Kicad, they are all rightly set with right 3d view in Kicad.

With a deeper observation, it seems that in Freecad, all vias more moved 2 layers below. But the holes are rightly located.

[qaqcvc]

I am using kicad 6 and 7 (test both), and Freecad 0.19

[qaqcvc]

Another board also has this issue, the only fix is to generate middle layers and top/bot layers separately and then merge. It would be great if we have a new version and solve this problem. Thank you!

[realthunder]

Is it possible to post a sample file showing the problem?

[qaqcvc]

Hi realthunder, thank you for checking! Please find one minimum test file here: test.zip

There are several issues in this practice:

1. I need to at least add one through via, otherwise it gives me error: line 991, in _makeArea
   if not force and obj[0].TypeId == 'Path::FeatureArea' and (
   <class 'IndexError'>: list index out of range
2. Normally when I select add via annular ring only for connected layers, all rings will be generated.
3. 1-2 micro vias and middle vias are on wrong positions
   
4. Wrong holes on top and bottom layers
   
   
5. Although successfully generate the 3d model but got error, this error occasionally occurs.
   line 11, in Part.show(coppers) <class 'TypeError'>: argument 1 must be Part.Shape, not Part.Feature

Thank you very much realthunder! As a hardware engineer, I tried to use chatgpt to find out possible solutions, but no good. If this issue can be solved, it would be really helpful for folks working on complex multiple layers design!

[realthunder]

Just added some fixes. Please sync the repo and test. You can close the issue if everything is fine.

[qaqcvc]

Hi realthunder, thanks for your reponse! From my side, the issue seems to consist:

Thank you for your precious time.

[realthunder]

Have you synced the repo, git pull maybe? Is the following model correct?

[qaqcvc]

Hi realthunder, Sorry I am not familiar with git, do not know why issue occurs when directly download the complete codes. When I only download kicad.py, it works! Now I do not need to seprately generate top,middle and bot layers.

But if the layout does not contain any through via, the fuse cannot be made. This issue can be escaped by mannually adding a dommy through via though.

And I constantly got this error:

It would be great if 'connected layers only' is implemented, which can largely reduce mesh complexity by removing unnecessary rings.

Thank you for your time!

[realthunder]

But if the layout does not contain any through via, the fuse cannot be made. This issue can be escaped by mannually adding a dommy through via though.

Please always provide a sample file showing the problem.

And I constantly got this error:

The macro code you are using is not mine. Is it hosted in some git repo so that I can take a look?

It would be great if 'connected layers only' is implemented, which can largely reduce mesh complexity by removing unnecessary rings.

Does that means the via is supposed to only have annular ring in the start and end layers?

[qaqcvc]

Please always provide a sample file showing the problem.
In you new added "blind_buried_vias.kicad_pcb" file, if you remove the only though hole via, the fuse will not be made.

The macro code you are using is not mine. Is it hosted in some git repo so that I can take a look?
I am using these codes:

from fcad_pcb import kicad
pcb = kicad.KicadFcad(r'C:\Users\25423\AppData\Roaming\FreeCAD\Macro\fcad_pcb\tests\blind_buried_vias.kicad_pcb')
pcb.add_feature = True

coppers = pcb.makeCoppers(shape_type='solid',holes=True,fuse=True)
Part.show(coppers)

Does that means the via is supposed to only have annular ring in the start and end layers?
For example, if vias are connected with layer 1,3,5... There should be no annular rings at layer 2,4.., because the fuse doesnot need to connect with these layers. The added annular rings only add unnecessary mesh elements. In my PCB design, there are more than 200 vias. The additional elements could bring addtional several hours of simulation.

[realthunder]

In you new added "blind_buried_vias.kicad_pcb" file, if you remove the only though hole via, the fuse will not be made.

This problem has been fixed. Please download kicad.py and try again.

And I constantly got this error:

Part.show() is for Shape not Feature. It is only necessary if pcb.add_feature = False, otherwise, there is no need to call that.

For example, if vias are connected with layer 1,3,5... There should be no annular rings at layer 2,4.., because the fuse doesnot need to connect with these layers.

Can you please make a sample file with this? It seems that KiCad has an option to remove unused vias/pads. Make sure to enable this option.

[qaqcvc]

Hi realthunder, thnak you! The first two issues are solved.
Regarding the last issue, please ref this file:
blind_buried_vias.zip
In this layout, there are two though vias, one has annular rings at all layers; while another one has annular rings only with connected layers.