Clock the PSoC 6 QSPI interface from the PLL

Author: aidangarske

hal/psoc6.c

@@ -139,7 +139,7 @@ static SMIF_Type* QSPIPort = SMIF0;
  *
  * SMIF Block - SMIF0
  */
-#define CY_SMIF_SYSCLK_HFCLK_DIVIDER (CY_SYSCLK_CLKHF_DIVIDE_BY_4)
+#define CY_SMIF_SYSCLK_HFCLK_DIVIDER (CY_SYSCLK_CLKHF_DIVIDE_BY_8)
 #define CY_SMIF_INIT_TRY_COUNT (10U)
 #define CY_SMIF_INIT_RETRY_DELAY_MS (500U)
 #define CY_SMIF_INIT_TIMEOUT_US (1000U)
@@ -290,7 +290,7 @@ static const cy_stc_smif_config_t QSPI_config = {
  *
  * Initialization steps:
  * 1. Configure QSPI data, clock, and slave-select GPIO pins
- * 2. Enable SMIF HF clock (CLK_HF2) with divide-by-4
+ * 2. Enable SMIF HF clock (CLK_HF2) from the PLL with divide-by-8
  * 3. Initialize SMIF block in normal mode
  * 4. Enable SMIF block
  * 5. Initialize external memory configuration with retry
@@ -330,9 +330,10 @@ cy_en_smif_status_t hal_ext_flash_init(void)
     (void)Cy_GPIO_Pin_Init(qspi_SS_Port, qspi_SS_Pin, &qspi_ss_config);
     Cy_GPIO_SetHSIOM(qspi_SS_Port, qspi_SS_Pin, qspi_SS_Mux);
 
-    /* Step 2: Enable SMIF HF clock (CLK_HF2) sourced from CLK_PATH0 */
+    /* Step 2: Enable SMIF HF clock (CLK_HF2) from the PLL, 100 MHz / 8. The
+     * FLL on CLK_PATH0 keeps whatever the last loader left, even unlocked. */
     (void)Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH2,
-                                   CY_SYSCLK_CLKHF_IN_CLKPATH0);
+                                   CY_SYSCLK_CLKHF_IN_CLKPATH1);
     (void)Cy_SysClk_ClkHfSetDivider(CY_SYSCLK_CLKHF_IN_CLKPATH2,
                                     CY_SMIF_SYSCLK_HFCLK_DIVIDER);
     (void)Cy_SysClk_ClkHfEnable(CY_SYSCLK_CLKHF_IN_CLKPATH2);

tools/unit-tests/unit-psoc6-qspi.c

@@ -136,12 +136,24 @@ void mock_set_hsiom(GPIO_PRT_Type *base, uint32_t pinNum, en_hsiom_sel_t value)
 cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum,
     const cy_stc_gpio_pin_config_t *config)
 { (void)base; (void)pinNum; (void)config; INIT_ONLY(); return CY_GPIO_SUCCESS; }
+static uint32_t smif_clk_src;
+static uint32_t smif_clk_div;
 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf,
     cy_en_clkhf_in_sources_t source)
-{ (void)clkHf; (void)source; INIT_ONLY(); return CY_SYSCLK_SUCCESS; }
+{
+    INIT_ONLY();
+    if (clkHf == 2U)
+        smif_clk_src = (uint32_t)source;
+    return CY_SYSCLK_SUCCESS;
+}
 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf,
     cy_en_clkhf_dividers_t divider)
-{ (void)clkHf; (void)divider; INIT_ONLY(); return CY_SYSCLK_SUCCESS; }
+{
+    INIT_ONLY();
+    if (clkHf == 2U)
+        smif_clk_div = (uint32_t)divider;
+    return CY_SYSCLK_SUCCESS;
+}
 cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf)
 { (void)clkHf; INIT_ONLY(); return CY_SYSCLK_SUCCESS; }
 cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base,
@@ -186,6 +198,8 @@ static void setup(void)
     dev_sfdp_0.memSize = QSPI_SIZE;
     smif_blk_config = &smifBlockConfig_sfdp;
     in_init = 0;
+    smif_clk_src = 0xFFU;
+    smif_clk_div = 0xFFU;
 }
 
 START_TEST(test_write_maps_offset)
@@ -278,6 +292,16 @@ START_TEST(test_init_checks_geometry)
 }
 END_TEST
 
+/* The SMIF clock comes from the PLL that wolfBoot sets up, never the FLL */
+START_TEST(test_init_clocks_smif_from_pll)
+{
+    in_init = 1;
+    ck_assert_int_eq(hal_ext_flash_init(), CY_SMIF_SUCCESS);
+    ck_assert_uint_eq(smif_clk_src, (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1);
+    ck_assert_uint_eq(smif_clk_div, (uint32_t)CY_SYSCLK_CLKHF_DIVIDE_BY_8);
+}
+END_TEST
+
 START_TEST(test_geometry)
 {
     ck_assert_int_eq(psoc6_qspi_geometry_ok(0x40000U), 1);
@@ -301,6 +325,7 @@ Suite *psoc6_qspi_suite(void)
     tcase_add_test(tc, test_erase_whole_sectors);
     tcase_add_test(tc, test_erase_rejects_partial_sectors);
     tcase_add_test(tc, test_init_checks_geometry);
+    tcase_add_test(tc, test_init_clocks_smif_from_pll);
     tcase_add_test(tc, test_geometry);
     suite_add_tcase(s, tc);
     return s;